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Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits.

In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment.

Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits.

The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

With continuous scaling of digital circuit CMOS technology, the vulnerability of these circuits are significantly increasing against the soft errors. On the other hand, the effects of process variation in the electrical properties of nano-scale circuits, have introduced the statistical methods as an unavoidable choice for the soft error rate (SER) estimation. The purpose of this paper is to provide a statistical soft error rate (SSER) estimation approach for combinational circuits in the presence of process variation.

In this paper a new method is proposed for the SSER estimation of combinational circuits based on the Bayesian networks (BNs). This allows to factor the joint probability distributions over variables in a circuit graph. The distribution of the initial transient fault pulse is estimated by the pre-characterization tables. Timing signals are propagated by BN theory and the probability distribution of electrical and timing masking are calculated.

Simulation results for some benchmark circuits show that the proposed method is accurate with 3.7 percent difference with the Monte-Carlo SPICE simulation and with orders of magnitude improvement in runtime.

The proposed framework is the scheme giving the low estimation time with plausible accuracy compared to other schemes. The comparison exhibits that the designer can save its estimation time in terms of performance and complexity. The deterministic-based methods also are able to evaluate the SER of combinational circuit, yet in an unacceptable time.